IBM today announced that it has developed a new method for building microchips that can deliver up to a 30 percent boost in computing speed and performance.

IBM's new manufacturing technique uses a material known as a "low-k dielectric" to meticulously shield millions of individual copper circuits on a chip, reducing electrical "crosstalk" between wires that can hinder chip performance and waste power.

The company is putting the technology to work immediately, designing custom chips that meet the high performance and low power consumption demands of next-generation networking equipment and Internet servers. The first chips built with this new process are expected to be available next year.

"This represents a fundamental shift in the way chips are built," said John Kelly, general manager of the IBM Microelectronics Division. "Along with the move from aluminum to copper to improve chip wiring, we believe this will help IBM maintain a one- to two-year lead over the rest of the industry."

Today, designers work to improve chips by adding more circuits and packing them closer together on a single piece of silicon. Limits are reached as those closely-packed circuits start to generate interference in one another — just as crosstalk can occur on telephone lines. IBM has developed a recipe for building chips with a "low-k dielectric," a material that forms a better seal around the chip's wiring, helping electronic signals move faster.

While IBM's technique is proprietary, the low-k material is a commercially available SiLK™ semiconductor dielectric produced by The Dow Chemical Company. In addition, IBM uses mainstream "spin-on" semiconductor manufacturing equipment to apply the material. The use of both materials and tooling that are generally available help make this the first technically and economically viable low-k process for copper chip fabrication.

To speed the introduction of products based on this new manufacturing process, IBM also announced today a custom chip offering called Cu-11. This application specific integrated circuit (ASIC) template will be manufactured with IBM's 0.13 micron process technology, resulting in chip features as small as .11 microns (more than 900 times thinner than a human hair). Cu-11 supports designs up to an unprecedented 40 million "gates," or circuits.

Cu-11 is expected to strengthen IBM's position as a leading worldwide ASIC supplier. According to 1999 market share figures from Dataquest, IBM has risen from the #2 to #1 worldwide supplier of standard-cell ASICs.

IBM plans to make Cu-11 design kits, including software design tools and services, available in July to help customers build a new generation of customized chips capable of driving high-performance Internet servers, power-saving cellular telephones, and advanced network communications gear.

In addition to custom chips, this new manufacturing technique will be used to produce future generations of the IBM Power4 processor, which is intended for use in IBM's RS/6000 and AS/400 server brands.

This milestone in semiconductor manufacturing was achieved after more than five years of collaboration between IBM's Microelectronics and Research divisions at the IBM Semiconductor Research and Development Center (SRDC) in Fishkill, NY. IBM is already producing chips with its new low-k process on an SRDC pilot production line and plans to introduce the technology on its high-volume Burlington, VT, manufacturing lines in the first half of 2001.